Digital visual interface and high-definition multimedia interface are high speed serial interconnect standards to transmit graphical data from a source to some type of display. The standards operate over a large range of data rates at very low differential voltage levels. The interface connection is limited to relatively short distance due to the combination of high data rates (250 Mb/s to 1.65 GB/s), low voltage swings (800 mV), reflections with the signal due to cable and connectors, and compatibility issues between manufactures of the transmitters and receivers.
FIG. 1 illustrates an example of this conventional system. In FIG. 1, a digital video source 20 is connected to a display device 30 through a cable 1. This system requires a specialize interface to establish a link between the source 20 and display 30.
With respect to another example of a conventional digital visual interface and/or high-definition multimedia interface system, the data transfer system sends data back and forth from point A to point B; however, the data transfer system does not send the same amount of data in one direction as in the other direction. More specifically, in the conventional system, Point A could be sending data at 2 Gb/s to point B, but Point B is only sending 1 Mb/s of data to Point A. Typically, this type of system would require two channels, one for the high speed downstream data and one for low speed upstream data, or a single mode system that creates bi-directional data stream, which adds additional circuitry.
Moreover, graphic applications operate at different clock rates for different display resolutions. However, in many data transfer architectures it is beneficial to transmit the data at a fixed data rate. The problem in realizing this benefit is providing an adequate conversion of the variable rate data being received by the converter to a fixed data rate for actual transmission, and then a conversion of the fixed rate data back to a variable rate data without loss.
In providing a digital visual interface and/or high-definition multimedia interface system, the integrated circuits associated with the interfaces need to be tested to ensure proper signal quality. Moreover, this testing needs to be done at operational speeds to ensure that the testing procedures can reliably identify problems.
There are several problems associated with testing the integrated circuits associated with the digital visual interface and/or high-definition multimedia interfaces. More specifically, one problem with testing of 1.65 GHz signals is using a generic digital tester. At gigahertz frequencies, it is difficult to produce quality signals over process, temperature, and voltage using CMOS-only chips.
More particularly, in the case of a high-definition multimedia interface, several signal quality specifications must be met in regards to rise times, fall times, jitter, duty cycle, etc. Any test circuit output loading, which results in degradation of signal quality, must be kept at a minimum since normal operation must not be adversely affected.
Another problem associated with testing the integrated circuits associated with the digital visual interface and/or high-definition multimedia interfaces is that a conventional sampled-data muxing circuit, such as a sample-and-hold, cannot be used. Conventional sample-muxing circuits; i.e., the circuit connecting the output drivers to the test circuit; does not operate in a continuous-time mode nor have a high bandwidth.
Moreover, the test circuitry must be high speed, small in area since it is not used in normal operation, robust so that chip yields do not suffer, and have a higher accuracy than the output stage so that false test failures are not generated. Conventionally if the test circuitry can meet the high speed requirement, the conventional test circuitry is not robustness, small area, or accurate.
A further problem associated with testing the integrated circuits associated with the digital visual interface and/or high-definition multimedia interfaces is the relatively high external termination voltage. For high-definition multimedia interfaces, the termination voltage is 3.3V, while the conventional chip supply voltage is 1.8V. Furthermore, the mux circuit must be able to operate at an input voltage of 3.3V, while being controlled by 1.8V logic. This voltage difference can negatively impact both normal operations and chip power-down because the voltage disparity can cause current to be drawn from the output pads by the mux. Also, conventional test circuitry is not able to process signals with a common-mode voltage higher than the 1.8V circuit supply voltage with good accuracy and without device failure due to high voltage fields.
Additionally, conventional test circuitry must be provided electrostatic discharge protection which generally lowers the frequency response of the circuitry. When providing a high speed test path, gates of a conventional mux circuit cannot be used in the signal path of the outputs to the sampling circuit since gates are CMOS devices. A CMOS device gate can only be connected to such an output pad through resistors. Since the resistors are large to prevent the test circuit from causing electrostatic discharge failures, the electrostatic discharge protection resistors lower the signal bandwidth. Thus, the electrostatic discharge problem limits circuit topologies for the mux circuit.
Thus, it is desirable to a testing circuitry which will not have a negative impact upon normal circuit behavior. Moreover, it is desirable to a testing circuitry which will not have an electrostatic discharge problem. Furthermore, it is desirable to a testing circuitry which will have a small area, be accurate, and robust. Also, it is desirable to a testing circuitry which is capable of making measurements of signals having voltages greater than the chip supply. Lastly, it is desirable to a testing circuitry which provides high and low speed functional testing of an analog dynamic signal path.